1. Field of the Invention
The present invention relates to a semiconductor memory device comprising a plurality of easily-controllable memory cells which can be accessed at high speed.
2. Description of the Prior Art
A conventional, standard, general-purpose DRAM has a page mode for access at a high speed cycle time. As is commonly known, in this page mode it is possible to access specified memory cells in a row of a memory cell array selected by means of a row address, by arbitrarily changing a column address in a string of simultaneously sensed memory cells.
High speed access is possible with this type of mode for the following reasons. Considerable time is required for sense amplification of the cell data in a DRAM, but once the data has been sensed, the read-out of this data proceeds very quickly. Once a column address has been changed in the page mode operation, the access to the sense amplifier which has sensed that cell is commenced and the data is output when a CAS signal is switched to "L." Accordingly, the page mode is a random access mode.
Recently, the capacity of memory chips has been increasing, year after year. Accordingly, the number of chips used in a system has been more reduced. Therefore, when large volume chips are used in the prior art, namely when many chips are used in the system, these chips are divided into a number of groups which are interleaved, making it possible to construct and utilize a memory system in which the apparent cycle time is short, but this method cannot be used to a system having small volume chips.
On the other hand, the speed of an MPU has been increasing year after year, and even in a small scale system there is a strong necessity to achieve high speeds. For these reasons, it has become necessary for a memory to operate at even higher cycle speeds. Also, from these requirements it is not absolutely necessary for the access operation to be random; there are many cases in which all that is required is the ability to read or write a string of data at high speed.
A method for providing a high speed operation for RAM including SRAM and the like has been reported in the following literature.
Chikai Ohno. "Self-Timed RAM: STRAM", FUJITSU Sci. tech. J., 24, 4, pp293-300, December 1988. PA1 a memory cell group comprising a plurality of memory cells arranged in matrix; PA1 specification means for specifying sequentially memory cells addressed by consecutive addresses in the memory cells, and for enterring them in an active state; PA1 data input/output (I/O) means for performing a data read-out/write-in operation (data I/O operation) for the consecutive memory cells specified by the specification means under a control based on a read-out/write-in signal provided from an external section; PA1 count means for counting the number of cycles of a basic clock signal provided from an external section; and PA1 control means for receiving at least one or more specification signals provided from an external section. PA1 for outputting a control signal per specification signal for specifying a particular cycle as a starting cycle to count the number of the cycles of the basic clock signal, and PA1 for instructing the count means to count the number of counts of the basic clock signal based on the control signal, and for controlling a specification operation executed by the specification means and the data I/O operation of the data I/O means, so that the memory access operations for the memory cell group are controlled. PA1 a memory cell group comprising a plurality of memory cells grouped into a plurality of cell blocks arranged in matrix; PA1 selection means for outputting a selection signal provided based on a basic clock signal provided consecutively from an external section and an address signal for specifying an address of the cell block in order to select and activate the cell block by interleaving consecutively the memory cell blocks; PA1 specification means for specifying sequentially and activating the memory cells addressed by consecutive addresses in the memory cell block in accordance with the address signal and the selection signal for activating and enterring the cell block in an active state by the selection means; PA1 data input/output (I/O) means for performing a data read-out/write-in operation (data I/O operation) for the consecutive memory cells specified by the specification means under a control based on a read-out/write-in signal provided from an external section; PA1 count means for counting the number of cycles of the basic clock signal provided from an external section; and PA1 control means for receiving at least one or more specification signals provided from an external section. PA1 for outputting a control signal per specification signal for specifying a particular cycle as a starting cycle to count the number of the cycles of the basic clock signal, and PA1 for instructing the count means to count the number of counts of the basic clock signal based on the control signal, and for controlling a selection and activation operation executed by the selection means, a specification operation executed by the specification means and the data I/O operation executed by the data I/O means, so that by which the memory access operations for the memory cell group are controlled. PA1 a memory cell group comprising a plurality of memory cells arranged in matrix; PA1 specification means for specifying and activating at once a fixed number of the memory cells, as a package memory cell, addressed by consecutive addresses in the memory cells in accordance with a basic clock signal and an address signal provided from an external section; PA1 store means for storing temporarily data from or to the fixed number of the memory cells specified at once by the specification means; PA1 control means for carrying at once a data transfer operation between the fixed number of the memory cells specified at once by the specification means and the store means in accordance with the basic clock signal and the specification signal; PA1 data Input/output (I/O) means for executing sequentially a data read-out/write-in operation (data I/O operation) for the store means in accordance with the basic clock signal; and PA1 count means for counting the number of cycles of a basic clock signal, PA1 wherein the control means receives at least one or more specification signals provided from an external section, PA1 outputs a control signal per specification signal for specifying a particular cycle as a starting cycle to count the number of the cycles of the basic clock signal, PA1 instructs the count means to count the number of counts of the basic clock signal based on the control signal, PA1 controls a specification operation executed by the specification means and the data I/O operation of the data I/O means based on the number of the cycles including the number of the cycles at least two or more counted from the particular cycle by the count means, and PA1 so that the control means controls the memory access operations for the memory cell group.
In the literature, the following method is disclosed. A RAM (STRAM) operates in synchronization with a system clock, namely in the RAM, an address signal and R/W signals for a read-out or for write-in are received in synchronization with the clock signal at a timing, then at the next timing a content of the memory cell addressed by the address signal is output.
However, in this method the address signal must be provided every cycle of the system clock. Therefore there is a disadvantage that the access operation to a memory cell in the RAM cannot be followed to the period of the system clock when the period becomes high.
When a conventional page mode is used an address change is absolutely necessary. Therefore, it is impossible to operate with a higher access cycle time which is more than the time determined by the address control of the system. Speed increases for the memory access operation are therefore limited.
Control signals such as RAS signals and CAS signals must be supplied to the memory chip. These control signals are produced by the system. Accordingly, the control for supplying the control signals to the memory chip is an obstacle to providing a high speed operation with a memory system which includes an access means. In this case, the operation control of the system becomes so complex that it is difficult to use the control of the system.